Memory queue handling techniques for reducing impact of high-latency memory operations

ABSTRACT

Techniques for handling queuing of memory accesses prevent passing excessive requests that implicate a region of memory subject to a high latency memory operation, such as a memory refresh operation, memory scrubbing or an internal bus calibration event, to a re-order queue of a memory controller. The memory controller includes a queue for storing pending memory access requests, a re-order queue for receiving the requests, and a control logic implementing a queue controller that determines if there is a collision between a received request and an ongoing high-latency memory operation. If there is a collision, then transfer of the request to the re-order queue may be rejected outright, or a count of existing queued operations that collide with the high latency operation may be used to determine if queuing the new request will exceed a threshold number of such operations.

The present Application is a Continuation of U.S. patent application Ser. No. 13/290,702, filed on Nov. 7, 2011 and published as U.S. Patent Publication No. 20130117513 on May 9, 2013, and claims priority thereto under 35 U.S.C. §120. The disclosure of the above-referenced parent U.S. Patent Application is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is related to processing systems and processors, and more specifically to techniques for handling queuing of requests to memory devices that reduce the impact of high-latency memory operations such as refresh.

2. Description of Related Art

Present day memory controllers include substantial queuing mechanisms that facilitate forward queuing of memory requests. A command queue is used to store incoming requests, which are then processed and placed in a re-order queue, that permits issuing of memory operations that can be processed with overlap, such as accesses to different devices, or sub-arrays that can be accessed independently. By re-ordering operations, the memory bandwidth can be substantially improved over that of memories in which operations must be performed sequentially.

Memory controllers, in addition to providing access to the memory devices and using queues to improve throughput, must also queue accesses while portions of the memory are unavailable for access. Dynamic random-access memories (DRAMS) typically require substantial internally-timed or externally-timed refresh intervals, and memories in general such as static random-access memories (SRAMS) and DRAMS have other housekeeping logic that performs non-memory access housekeeping operations such as bus calibration operations, making some memory regions inaccessible for significant periods during which memory accesses must be queued.

It would therefore be desirable to provide a method of managing memory operations that improves performance of memory accesses, in particular when high-latency housekeeping operations such as DRAM refresh or bus calibration must be performed.

BRIEF SUMMARY OF THE INVENTION

The invention is embodied in a method that provides access to memory devices by a processor using a memory controller. The method is a method of operation of the memory controller.

The memory controller includes a memory operation queue in which memory access operations are buffered as they are received and a re-order queue in which operations are queued according to rules that help determine an order in which the memory operations can be completed without conflicts with other accesses or housekeeping operations such as bus calibration or DRAM refresh operations. The memory operation queue may represent the lowest level queuing structure in a cascade of queuing structures interposed between the processor cores and the memory interfaces. Control logic that manages transfer of memory operations to the re-order queue first determines whether the re-order queue has an entry available, and then determines whether the memory access up next for transfer to the re-order queue will conflict with a high-latency housekeeping operation. If a conflict will occur, the control logic holds off on transferring the memory access operation at the head of the memory operation queue and moves to the next oldest entry in the memory operation queue to find a candidate for transfer to the re-order queue. As an alternative to holding off the colliding requests out-right, a threshold number of such requests can be accepted in the re-order queue before the control logic begins to hold off queuing requests that collide with the high-latency housekeeping operations.

The foregoing and other objectives, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiment of the invention, as illustrated in the accompanying drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objectives, and advantages thereof, will best be understood by reference to the following detailed description of the invention when read in conjunction with the accompanying Figures, wherein like reference numerals indicate like components, and:

FIG. 1 is a block diagram illustrating a processing system in which techniques according to an embodiment of the present invention are practiced.

FIGS. 2A-2C depict different memory controller architectures in which techniques according to embodiments of the present invention can be practiced.

FIG. 3 is a block diagram illustrating details of a memory controller 25 in accordance with an embodiment of the present invention.

FIG. 4 is a flowchart depicting a method of managing memory access operations in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to memory controllers and other circuits and computer systems in which received memory accesses are buffered in a memory access queue and then transferred to a re-order queue, from which the memory access operations are issued out-of-order, improving memory access throughput. In order to reduce the impact of high-latency memory operations, which are generally housekeeping operations such as DRAM refresh and bus calibration events, which can take place in any type of memory in which environmental factors such as temperature and/or power supply voltage are taken into account by adjusting operating characteristics of the memory devices, by changing compensation for bus skew and delay, or by physically affecting the skew/delay. The present invention provides a mechanism for preventing the re-order queue, which is generally smaller than one or more memory access queues (buffers) that store memory access operations as they arrive at the memory controller's bus interface, from being filled with memory access operations that cannot be performed due to high latency memory operations that are underway.

Referring now to FIG. 1, a processing system in accordance with an embodiment of the present invention is shown. The depicted processing system includes a number of processors 10A-10D, each coupled to a memory controller/bridge 15A, 15B in conformity with an embodiment of the present invention. The depicted multi-processing system is illustrative, and processing system in accordance with other embodiments of the present invention include uni-processor systems having symmetric multi-threading (SMT) cores. Processors 10A-10D are identical in structure and include cores 20A-20B and cache/local storage 12, which may be a cache level, or a level of internal system memory. Processors 10A-10B are coupled to main system memory 14 by memory controller/bridge 15A, a storage subsystem 16, which includes non-removable drives and optical drives, for reading media such as a CD-ROM 17 forming a computer program product and containing program instructions implementing operating systems and other software for execution by processors 10A-10D, The illustrated processing system also includes input/output (I/O) interfaces and devices 18 such as mice and keyboards for receiving user input and graphical displays for displaying information. Processors 10C-10D are similarly coupled to main system memory 14, storage subsystem 16, which includes non-removable drives and optical drives, for reading media such as CD-ROM 17, by memory controller/bridge 15B. While the system of FIG. 1 is used to provide an illustration of a system in which the processor architecture of the present invention is implemented, it is understood that the depicted architecture is not limiting and is intended to provide an example of a suitable computer system in which the techniques of the present invention are applied.

Referring now to FIGS. 2A-2C configurations of memory controller circuits in accordance with various embodiments of the invention are shown. FIG. 2A depicts an arrangement in which a memory buffer integrated circuit (IC) 15A that includes a memory controller 25A and couples a processor 10 via a processor bus, e.g., a front-side bus (FSB) to memory devices 24 that may be, for example, dual in-line memory modules (DIMMs) containing DRAM storage. The arrangement of FIG. 2A is thus similar to the arrangement of FIG. 1, in which a separate memory controller is interposed between a processor and memory devices. FIG. 2B depicts an alternative arrangement in which techniques of the present invention may also be practiced, in which a memory buffer IC 15B is also interposed between a processor 11 and memory devices 24, but memory controller 25B is integrated within processor 11. FIG. 2C depicts yet another alternative in which processor 11A is coupled directly to memory devices 24 and in which memory controller 25C is integrated. The examples illustrated in FIGS. 2A-2C and described above are not exhaustive, and the memory operation buffers and control logic that will be described in further detail below are not limited as to location within particular devices that implement processors, memory, and the devices that couple them within a processing system according to embodiments of the present invention.

Referring now to FIG. 3, details of a memory controller 25 in accordance with an embodiment of the present invention is shown, circuits of which can be used to implement memory controllers 25A-25C, of FIGS. 2A-2C, respectively. Memory controller 25 includes a bus interface unit 32 that receives memory access operation commands from a bus that interfaces memory controller 25 to upstream cache/processor circuits, and delivers the memory access operations to a general purpose queue 34 (buffer) that stores the memory access operations as they are received. A queue controller 30 is coupled to bus interface unit 32 and manages transfer of the memory access operations between general purpose queue 34 and a re-order queue 36 that allows for out-of-order issue of memory operations to memory resource A 37A and memory resource B 37B. Re-order queue 36 generally has fewer entries available than general-purpose queue, since the logic required to support out-of-order issuance of memory operations into the memory resources 37A, 37B generally requires the application of rules to manage the re-ordered issue, as well as determining in advance of issuing the memory access operation, which device(s) and rank(s) are implicated by the operation. Re-order queue 36 is managed by another queue control circuit 38 that performs the scheduled issue of memory operations from re-order queue 36 that optimizes performance by reducing latency that would otherwise be present due to overlapping accesses to memory resource A 37A and memory resource B 37B, and/or by alternating accesses between memory resource A 37A and memory resource B 37B. Memory resource A 37A and memory resource B 37B may represent memory ranks or columns or other subdivision of memory and are only exemplary memory resources, since the number of memory resources present will generally be much greater than two, for example the number of memory resources may be the number of memory ranks present and supported by the memory subsystem.

A memory refresh and calibration control block 40 are depicted as located within memory controller 25 to initiate refresh operations and bus calibration operations within memory resource A 37A and memory resource B 37B. In accordance with an embodiment of the present invention, queue control 30 generates a control signal new_request after queue control 38 de-asserts control signal queue2_full, indicating that an entry is available in re-order queue 36 and if general purpose queue 34 contains an entry for which transfer should not be rejected due to a high-latency housekeeping operation taking place in one of memory resource A 37A and memory resource B 37B that would collide with the memory address(es) associated with the entry.

Queue control 38 provides control signals block_A and block_B that indicate that a high-latency operation is taking place in memory resource A 37A and memory resource B 37B, respectively. Queue control 30 uses control signals block_A and block_B to qualify whether or not to transfer a memory access operation to re-order queue 36 by asserting control signal new_request and providing the memory access operation over a bus connecting general purpose queue 34 to re-order queue 36. Alternatively, queue control 30 can issue the transfer, and queue control 38 can reject the transfer by responding with a retry indication, which provides an implementation in which, for example, general purpose queue 34 can be located within a first device such as a processor and re-order queue 36 can be located within a second device such as a memory device, which may be embodied in a configuration such as that depicted in FIG. 2C. Only two control signals block_A and block_B are illustrated for clarity, but in practice, a vector of block signals are provided (block_A, block_B, block_C, . . . ) one for each of a plurality of memory resources. The total number of block signals in the vector is determined by the maximum number of memory resources (ranks) that a particular memory subsystem supports.

Queue control 30 will assert control signal new_request only if control signal queue2_full is not asserted, and if an entry is available in general purpose queue 34 having a memory access operation address that does not collide with an address indicated by one of control signals block_A and block_B. Queue control 30 can rotate through entries in general purpose queue 34, holding entries for which collisions are present, while transferring other operations that do not collide with high-latency memory operations to re-order queue 36. Queue control 38 generates control signals block_A and block_B, when memory refresh and calibration control 40 has issued a high-latency housekeeping operation, such as a row refresh operation, that implicates ranks/sub-arrays within, or the entirety of, memory resource A 37A and memory resource B 37B. Timing information may be used by queue control 38 to de-assert control signals block_A and block_B in advance of the high-latency operation being completed, so that re-order queue 36 can start processing the operations that were previously held off due to anticipated collision with the high-latency operation. Alternatively, or in combination, timing information may also be used by queue control 38 to start holding off memory access operations in advance of the high-latency operation actually commencing, in order to attempt to avoid having any colliding entries within re-order queue 36. In accordance with yet another embodiment of the invention, queue control 38 can also maintain a count of memory access operations within re-order queue that collide with a high-latency operation underway, determine whether the count is greater than a threshold to determine whether to accept any other colliding memory access operations, thus permitting only a predetermined number of memory access operations that collide with the high-latency operation to be present in re-order queue 36.

Referring now to FIG. 4, a method of controlling memory access in accordance with an embodiment of the present invention is illustrated in a flowchart. A memory access request is received for rank n (step 50). If the re-order queue is full (step 52), or a high-latency operation is underway in rank n (step 54), then the request is held in the upper queue (step 56). If the re-order queue is not full (step 52) and no high-latency operation is underway in rank n (step 54), then the request is posted to the re-order queue (step 58). Until the system is shut down (step 59) the method of steps 50-58 are repeated to handle incoming memory accesses.

While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form, and details may be made therein without departing from the spirit and scope of the invention. 

What is claimed is:
 1. A method of managing a queuing of access requests to one or more memory devices, the method comprising: receiving a memory access operation specifying an address; queuing the memory access operation in a memory access queue, in which memory operations are queued according to the order in which they are received; determining whether a high latency maintenance operation is being performed in a region of memory that includes the address; responsive to determining that no high latency maintenance operation is being performed in the region of memory that includes the address, transferring the memory access operation to a re-order queue from which multiple pending memory operations are issued out-of-order; and responsive to determining that a high latency maintenance operation is being performed in the region of memory, rejecting transferring the memory access operation to the re-order queue, whereby the transfer will be attempted at a subsequent time.
 2. The method of claim 1, further comprising responsive to determining that the re-order queue has an open entry, performing the determining whether the high latency maintenance operation is being performed, and only if no high latency memory operation is being performed in the region of memory, transferring the memory access operation to the re-order queue.
 3. The method of claim 2, wherein the determining further determines whether the re-order queue contains a threshold number of memory access operations specifying an address within the region of memory, and wherein the rejecting transferring the memory access operation is performed only if the re-order queue is full or the re-order queue already contains the threshold number of memory access operations specifying an address within the region of memory.
 4. The method of claim 3, wherein the threshold number of memory access operations is zero, wherein the transferring of any memory access operation specifying an address within the region of memory is rejected.
 5. The method of claim 1, wherein the high latency memory operation is a refresh operation.
 6. The method of claim 1, wherein the high latency memory operation is a bus calibration interval.
 7. The method of claim 1, wherein the determining further determines whether the re-order queue contains a threshold number of memory access operations specifying an address within the region of memory, and wherein the rejecting the transferring of the memory access operation is performed only if the re-order queue is full or the re-order queue already contains the threshold number of memory access operations specifying an address within the region of memory.
 8. The method of claim 3, wherein the threshold number of memory access operations is zero, wherein transfer of any memory access operation specifying an address within the region of memory is rejected.
 9. The method of claim 1, wherein the receiving a memory access operation is performed by a memory controller, and wherein the rejecting the transferring comprises issuing a retry operation response from a re-order queue controller.
 10. The method of claim 9, wherein the memory controller is integrated within a processor integrated circuit, and wherein the retry operation and the memory access operation are issued on an internal bus of the processor integrated circuit. 